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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? 8 1/10 mbps serial port s direct interface with home pna phy or 8 10/100 mbps rmii ports ? ideal for mdu (multiple dwelling unit) application with home pna phy ? 1 10/100 mbps auto-negot iating mii/serial port (port 8) that can be used as uplink port ? up to 8 port-based vlans can be configured from eeprom ? internal 1 k mac address table - auto address learning - auto address aging ? leading edge qos capabilities provided based on 802.1 p and ip tos/ds field - 2 queues per output port - packet scheduling based on weighted round- robin (wrr) - weighted random early detection/drop (wred) to drop packets during traffic congestion - 2 levels of packet drop provided ? supports both full/half duplex ports ? full wire-speed layer 2 switching on all ports ? ability to support winsock 2.0 and windows 98 & windows 2000 smart applications ? transmit delay control capabilities - provides maximum delay guarantee (<1 ms)(last bit in to first bit out) - supports mixed voice-data networks ? support concentrator mode ? ports 0 & 1 can be trunked to provide a 2x1/10 mbps link to another switch or server ? utilizes a single low-cost external pipelined, syncburst sram (sbram) for buffer memory - 56 k bytes or 512 k bytes (1 chip) ?external i 2 c eeprom for power-up configuration ? support external parallel port for configuration updates ? optimized pin-out for easy board layout ? packaged in a 208 pqfp november 2003 ordering information MVTX1100al 208 pin pqfp -40 c to +85 c MVTX1100 9-port home pna packet concentrator data sheet figure 1 - system block diagram MVTX1100 cpu s s r a m home pna phy home pna phy 1/10mb* serial interface 8 port home pna + 1-port mii switch 10/100 mii 9-port home pna packet concentrator * also supports 10/100mb rmii interface
MVTX1100 data sheet 2 zarlink semiconductor inc. description the MVTX1100 is a fully integrated 9-port ethernet packet concentrator designed to support home networking. it is ideal for multiple dwelling units (mdu) application. the MVTX1100 provides features no rmally not associated with plug-and-play technology without requiring an exte rnal processor to facilitate their utilization. the MVTX1100 begins operating immediately at power-up, learning addresses automatically and forwarding packets at full wire speed to any of its 8 output ports or the uplink expansion port. at power-up, MVTX1100 configures itself from the eeprom, and can then provide port trunking, port-based vlans, and quality of service (qos) capabilities, usually associated only with managed switches. the proprietary built-in intelligence of the MVTX1100 allows it to recognize and offer packet prioritization qos. packets are prioritized based on their layer 2 vlan priori ty tag or layer 3 type-of service/ differentiated services (tos/ds) field. this priority can be defined as transmit and/or drop priority. the MVTX1100 can be used to create an 8-port unmana ged switch with one wan router port by adding a cpu (arm or mpc 850) connected to the additional mii port (port 8). the only external components needed for a low cost mdu system are the home pna physical laye r transceivers and a single sbram per MVTX1100. operating at 50 mhz internally, and with a 50 mhz interface to the external sbram, the MVTX1100 sustains full wire-speed switching on all 9 ports. when the system supports 8 ports of 1 m home pna phy with the 10m serial uplink, the system clock can be operated to 20 mhz and still achieve full wire-speed switchin g on all nine ports. the chip is packaged in a small 208 pin plastic quad flat-pak (pqfp) package.
MVTX1100 data sheet 3 zarlink semiconductor inc. MVTX1100 physical pinout 184 186 188 190 192 194 196 198 200 202 204 206 208 74 76 78 12 10 8 6 4 2 72 70 68 66 64 62 60 58 56 54 14 32 30 28 26 24 20 18 16 22 34 52 50 48 46 44 40 38 36 42 m4_link m4_duplex m5_cls m5_link m5_duplex vdd m4_txen m4_txd m4_txclk m4_crs_dv m4_rxd m4_rxclk vss m5_txen m5_txd m5_txclk m5_crs_dv m5_rxd vss m6_txd m6_txclk m6_crs_dv m6_rxd m6_rxclk m3_duplex m3_link m3_cls m2_duplex m2_link m2_cls vss (core) m3_rxclk m3_rxd m3_crs_dv m3_txclk m3_txd vdd (core) m2_rxclk m2_rxd m2_crs_dv m2_txclk m3_txen m2_txd m2_txen vss m1_rxclk m1_rxd m1_crs_dv m1_txclk m1_txd m1_txen vdd m0_rxclk m0_rxd m0_crs_dv m0_txclk m0_txd m0_txen vss (core) m1_duplex m1_link m1_cls m0_duplex m0_link m0_cls vdd l_a[13] l_a[14] l_a[12] vss l_a[11] l_a[10] l_a[9] vdd_core l_a[8] l_a[7] la_[6] vss l_a[5] l_a[4] l_a[18] l_d[31] l_d[30] l_d[29] vss (core) l_d[28] l_d[27] l_d[26] vdd l_d[25] l_d[24] l_d[23] l_d[22] vss l_d[21] l_d[20] l_d[19] l_d[18] vdd (core) rmii port interfaces 182 180 178 176 174 172 170 168 166 164 162 160 158 84 82 80 146 148 150 152 154 156 86 88 90 92 94 96 98 100 102 104 144 126 128 130 132 134 138 140 142 136 124 106 108 110 112 114 118 120 122 116 m7_txen m7_txd m7_txclk m7_crs_dv m7_rxd m7_rxclk vdd m6_cls m6_link m6_duplex m7_cls m7_link m7_duplex vss m_clk vdd (core) m8_rxdv m8_col m8_rxclk vdd m8_rxd[0] m8_rxd[1] m8_rxd[2] m8_rxd[3] vss (core) m8_txclk vdd m8_txen m8_txd[0] m8_txd[1] m8_txd[2] m8_txd[3] m8_link m8_duplex m8_refclk vdd m_mdc vss scl test# trunk_en strobe data0 ack vdd (core) tstout[0] tstout[1] tstout[2] tstout[3] tstout[4] tstout[6] tstout[7] t_mode vss (core) rstout# mir_ctl[0] mir_ctl[2] mir_ctl[3] sclk vdd vss l_a[2] l_a[17] vdd l_clk vss l_we# l_d[16] vss l_d[14] l_d[13] l_d[12] l_d[11] vdd l_d[10] l_d[9] l_d[8] vss (core) l_d[7] l_d[6] l_d[5] l_d[4] vdd l_d[3] l_d[1] l_d[0] l_a[15] vdd (core) l_a[16] l_adsc# m4_cls m6_txen vss (core) vdd (core) l_a[3] vdd l_d[17] l_d[15] l_d[2] vss l_oe# mir_ctl[1] rstin# tstout[5] sda m_mdio vss m8_speed buffer mem interface config interfaces rmii port interfaces + pin 1 i.d. m5_rxclk mii port interfaces
MVTX1100 data sheet 4 zarlink semiconductor inc. pin reference table pin # pin name 1l_a[7] 2l_a[8] 3vdd (core) 4l_a[9] 5l_a[10] 6 l_a[11] 7 vss 8l_a[12] 9l_a[13] 10 l_a[14] 11 vdd 12 m0_cls 13 m0_link 14 m0_duplex 15 m1_cls 16 m1_link 17 m1_duplex 18 vss (core) 19 m0_txen 20 m0_txd/(m0_txd[0]) 1 21 m0_txclk/(m0_txd[1]) 22 m0_crs_dv 23 m0_rxd/(m0_rxd[0]) 24 m0_rxclk/(m0_rxd[1]) 25 vdd 26 m1_txen 27 m1_txd/(m1_txd[0]) 28 m1_txclk/(m1_txd[1]) 29 m1_crs_dv 30 m1_rxd/(m1_rxd[0]) 31 m1_rxclk/(m1_rxd[1]) 32 vss 33 m2_txen 34 m2_txd/(m2_txd[0]) 35 m2_txclk/m2_txd[1]) 36 m2_crs_dv 37 m2_rxd/(m2_rxd[0]) 38 m2_rxclk/ (m2_rxd[1]) 39 vdd (core) 40 m3_txen 41 m3_txd/(m3_txd[0]) 42 m3_txclk/(m3_txd[1]) 43 m3_crs_dv 44 m3_rxd/(m3_rxd[0]) 45 m3_rxclk/(m3_rxd[1]) 46 vss (core) 47 m2_cls 48 m2_link 49 m2_duplex 50 m3_cls 51 m3_link 52 m3_duplex 53 m4_cls 54 m4_link 55 m4_duplex 56 m5_cls 57 m5_link 58 m5_duplex 59 vdd 60 m4_txen 61 m4_txd/(m4_txd[0]) 62 m4_txclk/(m4_txd[1]) 63 m4_crs_dv 64 m4_rxd/(m4_rxd[0]) 65 m4_rxclk/(m4_rxd[1]) 66 vss 67 m5_txen 68 m5_txd/(m5_txd[0]) 69 m5_txclk/m5_txd[1]) 70 m5_crs_dv 71 m5_rxd/(m5_rxd[0]) 72 m5_rxclk/ (m5_rxd[1]) 73 vdd (core) 74 m6_txen 75 m6_txd/(m6_txd[0]) 76 m6_txclk/ (m6_txd[1]) 77 m6_crs_dv 78 m6_rxd/(m6_rxd[0]) 79 m6_rxclk/ (m6_rxd1]) 80 vss (core) 81 m7_txen 82 m7_txd/(m7_txd[0]) 83 m7_txclk/(m7_txd[1]) 84 m7_crs_dv 85 m7_rxd/(m7_rxd[0]) 86 m7_rxclk/(m7_rxd[1]) 87 vdd 88 m6_cls 89 m6_link 90 m6_duplex 91 m7_cls 92 m7_link 93 m7_duplex 94 vss 95 m_clk 96 vdd (core) 97 m8_rxdv/s8_crs_dv 98 m8_col/s8_col 99 vss 100 m8_rxclk/s8_rxclk 101 vdd 102 m8_rxd[0]/s8_rxd 103 m8_rxd[1]
MVTX1100 data sheet 5 zarlink semiconductor inc. note 1: pin names inside ( ) indicate rmii pins for ports 0-7. 104 m8_rxd[2] 105 m8_rxd[3] 106 vss (core) 107 m8_txclk/s8_txclk 108 vdd 109 m8_txen[0]/s8_txen 110 m8_txd[0]/s8_txd 111 m8_txd[1] 112 m8_txd[2] 113 m8_txd[3] 114 m8_link/s8_link 115 m8_duplex/s8_duple x 116 m8_speed 117 vss 118 m8_refclk 119 vdd 120 m_mdc 121 vss 122 m_mdio 123 scl 124 sda 125 test# 126 trunk_enable 127 strobe 128 data0 129 ack 130 vdd (core) 131 tstout[0] 132 tstout[1] 133 tstout[2] 134 tstout[3] 135 tstout[4] 136 tstout[5] 137 tstout[6] 138 tstout[7] 139 t_mode 140 vss (core) 141 rstout# 142 rstin# 143 (mirror_control[0]) 144 (mirror_control[1]) 145 (mirror_control[2]) 146 (mirror_control[3]) 147 vdd 148 sclk 149 vss 150 l_a[2] 151 l_a[17] 152 vdd 153 l_clk 154 vss 155 l_we# 156 l_oe# 157 l_adsc# 158 l_a[16] 159 vdd (core) 160 l_a[15] 161 l_d[0] 162 vss 163 l_d[1] 164 l_d[2] 165 l_d[3] 166 vdd 167 l_d[4] 168 l_d[5] 169 l_d[6] 170 l_d[7] 171 vss (core) 172 l_d[8] 173 l_d[9] 174 l_d[10] 175 vdd 176 l_d[11] 177 l_d[12] 178 l_d[13] 179 l_d[14] 180 vss 181 l_d[15] 182 l_d[16] 183 l_d[17] 184 vdd (core) 185 l_d[18] 186 l_d[19] 187 l_d[20] 188 l_d[21] 189 vss 190 l_d[22] 191 l_d[23] 192 l_d[24] 193 l_d[25] 194 vdd 195 l_d[26] 196 l_d[27] 197 l_d[28] 198 vss (core) 199 l_d[29] 200 l_d[30] 201 l_d[31] 202 vdd 203 l_a[18] 204 l_a[3] 205 l_a[4] 206 l_a[5] 207 vss 208 l_a[6]
MVTX1100 data sheet 6 zarlink semiconductor inc. figure 2 - system block diagram (high port density mdu system) MVTX1100 pal s s r a m home pna phy 10 mb serial interface switch chip 1-port mii 10/100 8-port 10 mb serial 10/100 mii line card 10/100 rmii mvtx2604 routing switch 24 10/100 ports + 2-1 g uplinks 192+2 port switch mdu system MVTX1100 64+1 port switch mdu system MVTX1100 s s r a m home pna phy home pna phy 1mb serial interface 8-port 1 mb serial line card home pna phy . . . 1 g gmii 10/100 mii 10 mbps serial interface
MVTX1100 data sheet 7 zarlink semiconductor inc. figure 3 - MVTX1100 block diagram 1 k
MVTX1100 data sheet 8 zarlink semiconductor inc. 1.0 functional operation the MVTX1100 was designed to provide a cost-effective layer 2 switching solution, using technology from the zarlink family to offer a highly integrated product for the unmanaged, diffserv read y, ethernet switching market. nine 1/10 media access controllers (mac) provide the prot ocol interface into the MVTX1100. these macs perform the required packet checks to ensure that each packet provi ded to the frame engine meets all the ieee 802.1 standards. data packets longer than 1518 (1522 with vlan tag) bytes and shorter than 64 bytes are dropped and MVTX1100 has been designed to support minimum inter-frame gaps between incoming packets. the phy addresses for the 8 rmii macs are from 08h to 0fh. these eight ports are denoted as ports 0 to 7. the phy address for the uplink mac is 10h. this port is denoted as port 8. the frame engine (fe) is the primary packet buffering and forwarding engine within the MVTX1100. as such, the fe controls the storage of packets in and out of the ex ternal frame buffer memory, keeps track of frame buffer availability and schedules output packet transmissions. while packet data is being buffered, the fe extracts the necessary information from each packet header and sends it to the search engine for processing. search results returned to the fe ensue the scheduling of packet transm ission and prioritization. when a packet is chosen for transmission, the fe reads the packet from external buffer memory and places it in the output fifo of the output port. 2.0 address l earning and aging the MVTX1100 is able to begin address learning and packet forwarding shortly after powerup has been completed. the search engine examines the contents of its internal switch database memory for each valid packet received on an input port. unknown source and destination mac addresses are dete cted when the search engine does not find a match within its database. these unknown source mac addresses are learned by creating a new entry in the switch database memory, and storing the necessary resulting info rmation in that location. subsequent searches to a learned destination mac address will return the new contents of that mac c ontrol table (mct) entry. after each source address search the mct entry aging fl ag is updated. mct entries that have not been accessed during a user configurable time period (2 to 67,108 se conds) will be removed. this aging time period can be configured using the 16-bit value stored in the regi sters mac address aging time low and high (matl[7:0], math[7:0]). the aging period is defined by the following equation: {math[7:0]&matl[7:0]} x 1024ms = tage the aging of all mct entries is checked once during each time period. if the mct entry has not been utilized before the end of the next time period, it will be deleted. note that when the system cl ock operates at 20 mhz, the aging period will be increased, compared with 50 mhz of system clock. one should ad just the math and mathl co ntent variable accordingly. 3.0 quality of service the MVTX1100 utilizes zarlink?s architecture that provid es a new level of (qos) capability to unmanaged switch applications. similar in operation to the qos capabilities of other zarlink chipset members, MVTX1100 provides two transmit queues per output port. the frame engine manages the output transmission queue s for all the MVTX1100 ports. once the destination address search is complete, and the s witch decision is passed back to the fe, the packet is inserted into the appropriate output queue. the packet entry into the high or low priority queue is controlled by either the vlan tag information or the type of service/differentiated service (t os/ds) field in the ip header. either of these priority fields can be used to select the transmission priority, and th e mapping of the priority field values into either the high or low priority queue can be configured us ing the MVTX1100 configuration registers.
MVTX1100 data sheet 9 zarlink semiconductor inc. if the system uses the tos/ds field to prioritize packets, there are two choi ces regarding which bits of the tos/ds field are used. bits [0:2] of the tos byte (known as the ip precedence field) or bits [3:5] of the tos byte (known as the drt field) can be used to map the transmission queue prio rity. either bits, [0:2] or [3 :5], can also be used as a packet drop precedence, by using bits 6 and 7 of the fcb buffer low threshold register (fcbst). MVTX1100 utilizes weighted round robin (wrr) and weighted random early detection/drop (wred) to schedule packets for transmission. to enable MVTX1100?s qos capabilities requires the use of an external eeprom to change t he default register configurations and turn on qos. weighted round robin is an efficient method to ensure th at each of the transmission queues gets at least a minimum service level. with two output transmission queues, MVTX1100 will transmit ?x? packets from the high priority queue before transmitting ?y? packets from the lo w priority queue. MVTX1100 allows the designer to set the high priority weight to a value between 0 and 16. the low prio rity weight is fixed at the value 1. if the high priority weight is set to the value 4, then it will transmit 4 high priority packets before transmitting each low priority packet. MVTX1100 also uses a proprietary mechanism to ensure the timely delivery of high priority packets. when the latency of high priority packets reaches a threshold, it will override the wrr weights and transmit only high priority packets until the high priority packet delays are below the threshold. this threshold limit is set at less than 1 ms (last bit in and first bit out). the qos capabilities of the MVTX1100 are enabled by lo ading the appropriate values into the configuration registers. qos for packet transmi ssion is enabled by performing the following four steps: 1. select the tos/ds or vlan priority tag field as the control for ip packet transmi ssion. the selection is made using bit 7 of the flooding control (fcr[7]) register. - fcr[7]=0, use vlan priority tag field to map the transmission priority if this tag field exists. - fcr[7]=1, use tos/ds field for ip packet transmission priority mapping. 2. select which tos/ds field to use as the control for pa cket transmission priority if the tos/ds field was selected in step 1. the selection is made using bit 6 of the fcb buffer low threshold (fcbst[6]) register. - fcbst[6]=0, use dtr subfield to map the transmission priority. - fcbst[6]=1, use ip precedence subfield 1 to map the transmission priority. 3. set the transmission queue weight for the high priority queue in the transmission scheduling control (axsc[3:0]) register. 4. set the priority mappings from the tos/ds or vlan priori ty tag field to the high or low priority output queue. the selection is made using the vlan priority ma p (avpm) and tos priority map (tospml) registers. note that, for half duplex operation, the priority queues 2 must be enabled using bit 7 in the transmission scheduling control (axsc[7]) register to utilize the qos function. when qos is enabled, MVTX1100 will utilize wrr to schedule packet transmission, and will use weighted random early detection/drop (wred) to drop random packets in order to handle buffer memory congestion. in this method, only certain packet flows are slowed down whil e the remaining see no impact from the network traffic congestion. weighted random early detection/drop (wred) is a method of handling traffic congestion in the absence of flow control mechanisms. when flow control is enabled, all devices that are connected to a switch node that is exercising flow control are effectively unable to transmit, including nodes that are not directly responsible for the congestion problem. this inability to transmit during flow control periods would play havoc with voice packets, or other high priority packet flows, and th erefore flow control is not recommended for networks that mix voice and data traffic. 1. ip precedence and dtr subfields are referred to as tos/ds[0:2] and tos/ds[3:5] in the ip tos/ds byte. 2. in half duplex mode, the qos functions are disabled by default.
MVTX1100 data sheet 10 zarlink semiconductor inc. wred allows traffic to continue flowing into ports on a switch, and randomly drops packets with different probabilities based upon each packet?s priority markings. as the switch congestion increases, the probability of dropping an input packet increases, and as congestion decreases, the probability of dropping an input packet decreases. in this manner, only traffic flows that have had packets dropped will be affected by the congestion. other traffic flows will see no effect. the following table summarizes the wred operation of the MVTX1100. it lists the buffer thresholds at which each drop probability takes effect. table 1 - wred operation of the MVTX1100 the wred packet drop capabilities of MVTX1100 are enabled by performing the following three steps: 1. select the tos/ds or vlan tag field as the control for packet dropping. the selection is made using bit 7 of the flooding control (fcr[7]) register. - fcr[7]=0, use vlan priority tag field to m ap the drop priority if this tag field exists - fcr[7]=1, use tos/ds field for ip packet transmission priority mappin. 2. select which tos/ds tag field to use for packet dropping provided that the tos/ds fi eld was selected in step 1. the selection is made using bit 7 of the fcb buffer low threshold (fcbst[7]) register. - fcbst[7]=0, use dtr subfield to map the drop priority - fcbst[7]=1, use ip precedence subfield to map the drop priority 3. set the drop mappings from the tos/ds or vlan tag field to the high or low drop priority output flag. the selec- tion is made using the vlan drop map (avdm) and tos discard map (tosdml) registers. note that to utilize the qos function of the MVTX1100, flow control has to be disabled. 4.0 buffer management MVTX1100 stores each input packet in to the external frame buffer memory while determining the destination the packet is to be forwarded to. the total number of packets that can be stored in the frame buffer memory depends upon the size of the external sbram that is utilized. for a 256 k byte sbram MVTX1100 can buffer 170 packets. for a 512 k byte sbram MVTX1100 can buffer 340 packets. in order to provide good qos characteristics, MVTX1100 mu st allocate the available buffer space to low and high priority unicast and multicast traffic. this can be accomplis hed using the external eepr om to load the appropriate values into MVTX1100 configuration registers. to allow the designer to set the minimum number of buffers provided for low drop priority unicast traffic, use the low drop pr iority buffer threshold (lpbt[7:0]) register. to set the maximum number of buffers allocated for all multicast packets, use the multicast buffer control (mbcr[7:0]) register. during operation MVTX1100 will continuously monito r the amount of frame buffer memory that is available, and when the unused buffer space falls below a designer configurable threshold, MVTX1100 will begin to drop incoming packets (wred). this threshold is set using the fcb buffer low threshold (fcbst[5:0]) register. wred threshold drop percentage condition for high priority queue condition for low priority queue drop percentage for high-drop packet drop percentage for low-drop packet level 0 total buffer space available in device is lpbt 50% 0% level 1 24 buffers occupied 72 buffers occupied 75% 25% level 2 84 buffers occupied 100% 50%
MVTX1100 data sheet 11 zarlink semiconductor inc. 5.0 virtual lans MVTX1100 provides the designer the ability to define a single port-based virtual lan (vlan) for each of the nine ports. this vlan is individually defined for each port using the port control registers (ecr1px[6:4]). bits [6:4] allow the designer to define a vlan id (value between 0-7) for each port. when packets arrive at an input of MVTX1100, the search engine will determine the vlan id for that port, and then determine which of the other ports also are members of that vlan by matching their assigned vlan id values. the packet will then be transmitted to each port with the same vlan id as the source port. 6.0 concentration mode MVTX1100 supports a concentration mode, where each of the 0-7 port is only allowed to directly communicate with the uplink port 8. this mode ensures that data from any of ports 0-7 cannot be directly seen by any other port. this feature is used in mdu applications to provide data privacy to subscribers. to use this mode, a conc (concentration) bit in each ecr1 register of ports 0-8 must be enabled, i.e., ecr1 [7]=1, and ports 0-7 must each be set on a separate vlan. note that, in concentration mode, the vlan of port 8 will be ignored. a more flexible concentration mode can be set up. for this mode, ports 0?7 are partitioned into several groups, sharing the same vlan id. this will allow traffic within the same group to freely communicate with each other, while continuing to communicate outside the group in concentration mode. 7.0 port trunking port trunking allows the designer to configure the mvtx11 00, such that ports 0 and 1 are defined as a logical port. this provides a 20mb/s link to a switch or server using two 10mb/s ports in parallel. ports 0 and 1 can be trunked by pulling the trunk_en pin to the high state. in this mode, the source mac address of all packets received from the trunk are checked against the mct database to ensure that they have a port id of 0 or 1. packets that have a port id other than 0 and 1 will effect the MVTX1100 to learn the new mac address for this port change. on transmission, the selected trunk port is determined by hashing the source and destination mac addresses. this provides a one-to-one mapping between the trunk port and the mac addresses. subsequent packets with the same mac addresses will always utilize the same trunk port. MVTX1100 also provides a safe fail-over mode for port trunking. if one of the two ports goes down, via the ports link signal, MVTX1100 will switch all traffic destined to the fa iled port over to the remaining port in the trunk. thus maintaining the trunk link, albeit at a lower effective bandwidth.
MVTX1100 data sheet 12 zarlink semiconductor inc. 8.0 port mirroring the port mirroring function is only supported in rmii mode. using the 4 port mirroring control pins provides the ability to enable or disable port mirroring, select which of the remaining 7 ports is to be mirrored and whether the received or transmitted data is being mirrored. the control for this function is shown in the following table. table 2 - port mirroring configuration when enabled, port mirroring will allow the user to monitor traffic going through the switch on output port 7. if the port mirroring control pins, mirror_cont rol[3:0], are left floating, MVTX1100 will operate with the port mirroring function disabled. when port mirroring is enabled, the user must configure port 7 to operate in the same mode as the port it is mirroring (autoneg, duplex, speed, flow control). 9.0 power saving mode in mac the power saving mode is activated only in rmii mode. MVTX1100 was designed to be power efficient. when the internal rmii mac sections detect that the external port is not receiving or transmitt ing packets, it will shut down and conserve power. when new packet data is loaded into the output transmit fifo of a mac in power saving mode, the mac will return to life and begin operating immediately. when the mac is in power saving mode and new packet data is received on the rmii interface, the mac will return to life and receive data normally into the receive fifo. this wake up occurs when the mac sees the crs_dv signal asserted. using this method, the switch will turn off all mac sections during periods when there is no network activity (at night for example), and save power. for large networks this pow er savings can be significan t. to achieve the maximum power efficiency, the designer should use a physical layer transceiver that utilizes ?wake-on-lan? technology. mirrored port mirror_control [3] mirror_control [2] mirror_control [1] mirror_control [0] port 0 rx 1 0 0 0 port 0 tx 0 0 0 0 port 1 rx 1 0 0 1 port 1 tx 0 0 0 1 port 2 rx 1 0 1 0 port 2 tx 0 0 1 0 port 3 rx 1 0 1 1 port 3 tx 0 0 1 1 port 4 rx 1 1 0 0 port 4 tx 0 1 0 0 port 5 rx 1 1 0 1 port 5 tx 0 1 0 1 port 6 rx 1 1 1 0 port 6 tx 0 1 1 0 disabled x 1 1 1
MVTX1100 data sheet 13 zarlink semiconductor inc. 10.0 eeprom i 2 c i nterface a simple 2 wire serial interface is provided to a llow the configuration of the mv tx1100 via an external eeprom. MVTX1100 utilizes a 1 k bit eeprom with an i 2 c interface. 11.0 management interface MVTX1100 uses a standard parallel port interface to provide external cpu access to the internal registers. this parallel interface consists of 3 pins: data0, strobe and ack. the data0 pin provides the address and data content input to MVTX1100, while the ack pin provides the corresponding output to the external cpu. the strobe pin is provided as the clock for both serial data streams. any of its inter nal registers can be modified through this parallel port interface. figure 4 - write command figure 5 - read command each management interface transfer consists of four parts: 1. a start pulse ? occurs when data is sampled high when strobe is rising followed by data being sampled low when strobe falls. 2. register address strobed into data0 pin by the high level of the strobe pin. 3. either a read or write command (see waveforms above). 4. data to be written provided on data0, or data to be read back provided on ack. any command can be aborted in the middle by sending an abort pulse to MVTX1100. an abort pulse occurs when data is sampled low and strobe is rising, then data is sampled high when strobe falls.
MVTX1100 data sheet 14 zarlink semiconductor inc. 12.0 configuration register definitions MVTX1100 registers can be accessed via the parallel interface and/or the i 2 c interface. some registers are only accessible through the parallel interface. the access method for each register is listed in the individual register definitions. each register is 8-bit wide. 12.1 gcr - global control register ? access: parallel interface, write only ? address: h30 12.2 dcr - device status and signature register ? access: parallel interface, read only ? address: h31 bit 0 save configuration into eeprom write '1' followed by a '0' (default = 0) bit 1 save configuration into eepr om and reset system write '1' (self-clearing due to reset) (default = 0) bit 2 start built-in self-test (bist) write '1' followed by a '0' (default = 0) bit 3 reset system write '1' (self-clearing due to reset) (default = 0) bit [7:4] reserved bit 0 busy writing configuration from i 2 c 1: activity 0: no activity bit 1 busy reading configuration from i 2 c 1: activity 0: no activity bit 2 built-in self-test (bist) in progress 1: bist in-progress 0: normal mode bit 3 ram error during bist 1: ram error 0: no error bit [5:4] reserved bit [7:6] revision number 00: initial silicon 01: second silicon
MVTX1100 data sheet 15 zarlink semiconductor inc. 12.3 da ? da register ? access: parallel interface, read only ? address: h36 always returns 8-bit valu e hda. indicates the (default da) parallel port connection is good. 12.4 mbcr ? multicast buffer control register (address h00) ? access: parallel interface and i 2 c, read/write ? address: h00 12.5 fcbst ? fcb buffer low threshold ? access: parallel interface and i 2 c, read/write ? address: h01 12.6 lpbt ? low drop priority buffer threshold ? access: parallel interface and i 2 c, read/write ? address: h02 12.7 fcr ? flooding control register ? access: parallel interface and i 2 c, read/write ? address: h03 bit [7:0] max_cnt_lmt maximum number of multicast frames allowed (default = 80) bits [5:0] buf_low_th buffer low threshold ? number of fcb left before triggering wred (default = 3f) bit 6 use ip precedence field (tos[0:2]) for priority (default = 0) bit 7 use ip precedence subfield (tos[0:2]) for drop (default = 0) note that, for bits 6 and 7, default = 0 means to use dtr filed (tos[3:5]). bit [7:0] low_pri_cnt number of frame buffers reserved for low-dropping traffic (default 3f) bits [3:0] u2mr unicast to multicast rate (default = 8) bits [6:4] timebase 000 = 100 s 001 = 200 s 010 = 400 s 011 = 800 s 100 = 1.6 ms 101 = 3.2 ms 110 = 6.4 ms 111 = 100 s (default = 000) bit 7 use_tos pick tos over vlan priority for ip packet. (default = 0)
MVTX1100 data sheet 16 zarlink semiconductor inc. 12.8 avtcl ? vlan type code register loq ? access: parallel interface and i 2 c, read/write ? address: h04 12.9 avtch ? vlan type code register high ? access: parallel interface and i 2 c, read/write ? address: h05 12.10 avpm ? vlan priority map ? access: parallel interface and i 2 c, read/write ? address: h06 12.11 avdm ? vlan discard map ? access: parallel interface and i 2 c, read/write ? address: h07 bit [7:0] vlantype_low lower 8 bits of vlan type code. (default 00) bit [7:0] vlantype_high upper 8 bits of the vlan type code (default 81) map vlan tag into 2 transmit queues (0 = low priority, 1 = high priority) bit 0 mapped priority of tag value 0 (default 0) bit 1 mapped priority of tag value 1 (default 0) bit 2 mapped priority of tag value 2 (default 0) bit 3 mapped priority of tag value 3 (default 0) bit 4 mapped priority of tag value 4 (default 0) bit 5 mapped priority of tag value 5 (default 0) bit 6 mapped priority of tag value 6 (default 0) bit 7 mapped priority of tag value 7 (default 0) map vlan tag into frame discard when low priority buffer usage is above threshold bit 0 frame discard for tag value 0 (default 0) bit 1 frame discard for tag value 1 (default 0) bit 2 frame discard for tag value 2 (default 0) bit 3 frame discard for tag value 3 (default 0) bit 4 frame discard for tag value 4 (default 0) bit 5 frame discard for tag value 5 (default 0) bit 6 frame discard for tag value 6 (default 0) bit 7 frame discard for tag value 7 (default 0)
MVTX1100 data sheet 17 zarlink semiconductor inc. 12.12 tospml ? tos/ds priority map low ? access: parallel interface and i 2 c, read/write ? address: h08 12.13 tosdml ? tos/ds discard map ? access: parallel interface and i 2 c, read/write ? address: h0a 12.14 axsc ? transmission scheduling control register ? access: parallel interface and i 2 c, read/write ? address: h0b map tos field in ip packet into 2 transmit queues (0 = low priority, 1 = high priority). bit 0 mapped priority when tos is 0 (default 0) bit 1 mapped priority when tos is 1 1 1. tos = 1 means the appropriate 3-bit tos subfield is ?001. (default 0) bit 2 mapped priority when tos is 2 (default 0) bit 3 mapped priority when tos is 3 (default 0) bit 4 mapped priority when tos is 4 (default 0) bit 5 mapped priority when tos is 5 (default 0) bit 6 mapped priority when tos is 6 (default 0) bit 7 mapped priority when tos is 7 (default 0) map tos into frame discard when low priority buffer usage is above threshold bit 0 frame discard when tos is 0 (default 0) bit 1 frame discard when tos is 1 (default 0) bit 2 frame discard when tos is 2 (default 0) bit 3 frame discard when tos is 3 (default 0) bit 4 frame discard when tos is 4 (default 0) bit 5 frame discard when tos is 5 (default 0) bit 6 frame discard when tos is 6 (default 0) bit 7 frame discard when tos is 7 (default 0) bits [3:0]: transmission queu e service weight for high priority queue (default f) bit [4] reserved bit [5] reserved bit [6]: global flow control (default 0, enable) bit [7]: half duplex priority enable (default 0)
MVTX1100 data sheet 18 zarlink semiconductor inc. 12.15 mii_op0 ? mii register option 0 ? access by parallel interface and i 2 c, read/write ? address: h0c to provide a non-standard address for the phy status register. when low and high address bytes are 0, MVTX1100 will use the standard address. bit [7:0] low order address byte (default 00) 12.16 mii_op1 ? mii register option 1 ? access: parallel interface and i 2 c, read/write ? address: h0d 12.17 agetime_low ? mac address aging timer low access: parallel interface and i 2 c, read/write address: h0e 12.18 agetime_high ? mac address aging timer high ? access: parallel interface and i 2 c, read/write ? address: h0f 12.19 ecr1p0 ? port 0 control register ? access: parallel interface and i 2 c, read/write ? address: h10 bit [7:0] high order address byte (default 00) bit [7:0] low byte of the mac address aging timer. (default 25) bit [7:0] high byte of the mac address aging timer. the aging time is based on the follow ing formula: {agetime_high, agetime_low} x 1024 ms. (default 01) bits [3:0] rmii port mode only for rmii mode, serial mode don?t care (default 0000) bit [0] 1 ? flow control off 0 ? flow control on bit [1] 1 ? half duplex 0 ? full duplex bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [3] 1 ? force configuration based on bits [2:0] 0 ? auto and advertise based on bits [2:0] bits [6:4] pvid port-base d vlan id (default 000) bit [7] conc: enable concentration mode
MVTX1100 data sheet 19 zarlink semiconductor inc. 12.20 ecr1p1 ? port 1 control register ? access: parallel interface and i 2 c, read/write ? address: h11 12.21 ecr1p2 ? port 2 control register ? access: parallel interface and i 2 c, read/write ? address: h12 bits [3:0] rmii port mode only for rmii mode, serial mode don?t care (default 0000) bit [0] 1 ? flow control off 0 ? flow control on bit [1] 1 ? half duplex 0 ? full duplex bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [3] 1 ? force configuration based on bits [2:0] 0 ? auto and advertise based on bits [2:0] bits [6:4] pvid port-base d vlan id (default 000) bit [7] conc: enable concentration mode (default 0) bits [3:0] rmii port mode on ly for rmii mode,(default 0000) serial mode don?t care (default 0000) bit [0] 1 ? flow control off 0 ? flow control on bit [1] 1 ? half duplex 0 ? full duplex bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [3] 1 ? force configuration based on bits [2:0] 0 ? auto and advertise based on bits [2:0] bits [6:4] pvid port-base d vlan id (default 000) bit [7] conc: enable concentration mode (default 0)
MVTX1100 data sheet 20 zarlink semiconductor inc. 12.22 ecr1p3 ? port 3 control register ? access: parallel interface and i 2 c, read/write ? address: h13 12.23 ecr1p4 ? port 4 control register ? access: parallel interface and i 2 c, read/write ? address: h14 bits [3:0] rmii port mode only for rmii mode, serial mode don?t care (default 0000) bit [0] 1 ? flow control off 0 ? flow control on bit [1] 1 ? half duplex 0 ? full duplex bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [3] 1 ? force configuration based on bits [2:0] 0 ? auto and advertise based on bits [2:0] bits [6:4] pvid port-base d vlan id (default 000) bit [7] conc: enable concentration mode (default 0) bits [3:0] rmii port mode on ly for rmii mode, (default 0000) serial mode don?t care (default 0000) bit [0] 1 ? flow control off 0 ? flow control on bit [1] 1 ? half duplex 0 ? full duplex bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [3] 1 ? force configuration based on bit [2:0] 0 ? auto and advertise based on bit [2:0] bits [6:4] pvid port-base d vlan id (default 000) bit [7] reserved enable concentration mode (default 0)
MVTX1100 data sheet 21 zarlink semiconductor inc. 12.24 ecr1p5 ? port 5 control register ? access: parallel interface and i 2 c, read/write ? address: h15 12.25 ecr1p6 ? port 6 control register ? access: parallel interface and i 2 c, read/write ? address: h16 bits [3:0] rmii port mode only for rmii mode, serial mode don?t care (default 0000) bit [0] 1 ? flow control off 0 ? flow control on bit [1] 1 ? half duplex 0 ? full duplex bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [3] 1 ? force configuration based on bit [2:0] 0 ? auto and advertise based on bits [2:0] bits [6:4] pvid port-base d vlan id (default 000) bit [7] conc: enable concentration mode (default 0) bits [3:0] rmii port mode only for rmii mode, serial mode don?t care (default 0000) bit [0] 1 ? flow control off 0 ? flow control on bit [1] 1 ? half duplex 0 ? full duplex bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [3] 1 ? force configuration based on bit [2:0] 0 ? auto and advertise based on bit [2:0] bits [6:4] pvid port-base d vlan id (default 000) bit [7] conc: enable concentration mode (default 0)
MVTX1100 data sheet 22 zarlink semiconductor inc. 12.26 ecr1p7 ? port 7 control register ? access: parallel interface and i 2 c, read/write ? address: h17 12.27 ecr1p8 ? port 8 control register ? access: parallel interface and i 2 c, read/write ? address: h18 bits [3:0] rmii port mode only for rmii mode, serial mode don?t care (default 0000) bit [0] 1 ? flow control off 0 ? flow control on bit [1] 1 ? half duplex 0 ? full duplex bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [3] 1 ? force configuration based on bit [2:0] 0 ? auto and advertise based on bit [2:0] bits [6:4] pvid port-base d vlan id (default 000) bit [7] conc: enable concentration mode (default 0) bits [3:0] port mode (default 0000) bit [3] 1 ? force configuration based on bit [2:0] 0 ? autonegotiate and advertise based on bit[2:0] bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [1] 1 ? half duplex 0 ? full duplex bit [0] 1 ? flow control off 0 ? flow control on bits [6:4] pvid port-base d vlan id (default 000) bit [7] conc: enable concentration mode (default 0)
MVTX1100 data sheet 23 zarlink semiconductor inc. 12.28 fc_0 ? flow control byte 0 ? access: parallel interface and i 2 c, read/write ? address: h19 the flow control hold time parameter is the length of time a flow control message is effectual (i.e. halts incoming traffic) after being received. the hold time is measured in units of ?slots,? the time it takes to transmit 64 bytes at wire speed. the default setting is 32 slots, or for a 100 mbps port, approximately 164 s. bits [7:0] flow control hold time byte 0 (default ff) 12.29 fc_1 ? flow control byte 1 ? access: parallel interface and i 2 c, read/write ? address: h1a bits [7:0] flow control hold time byte 1 (default 00) 12.30 fc_2 ? flow control crc byte 0 ? access: parallel interface and i 2 c, read/write ? address: h1b bits [7:0] flow control frame crc byte 0 (default 96) 12.31 fc_3 ? flow control crc byte 1 ? access: parallel interface and i 2 c, read/write ? address: h1c bits [7:0] flow control frame crc byte 1 (default 8e) 12.32 fc_4 ? flow control crc byte 2 ? access: parallel interface and i 2 c, read/write ? address: h1d bits [7:0] flow control frame crc byte 2 (default 99) 12.33 fc_5 ? flow control crc byte 3 ? access: parallel interface and i 2 c, read/write ? address: h1e bits [7:0] flow control frame crc byte 3 (default 9a) 12.34 checksum - eeprom checksum ? ? access: parallel interface and i 2 c, read/write ? ? address: h24 the calculation is [0x100 - ((sum of registers 0x00~0 x23) & 0xff)]. for example, based on the default register settings, the checksum value would be 0xee. bits [7:0] checksum (default 00)
MVTX1100 data sheet 24 zarlink semiconductor inc. 13.0 MVTX1100 pin descriptions note: # active low signal i input signal s input signal with schmitt-trigger o output signal od open-drain driver i/o input & output signal sl slew rate controlled d pulldown u pullup 5 5v tolerance pin no(s). symbol type name & functions frame buffer memory interface 201, 200, 199, 197, 196, 195, 193, 192, 191, 190, 188, 187, 186, 185, 183, 182, 181, 179, 178, 177, 176, 174, 173, 172, 170, 169, 168, 167, 165, 164, 163, 161 l_d[31:0] i/o, u, sl databus to frame buffer memory 203, 151, 158, 160, 10, 9, 8, 6, 5, 4, 2, 1, 208, 206, 205, 204, 150 l_a[18:2] i/o, u, sl address pins for buffer memory 153 l_clk o frame buffer memory clock 155 l_we# o, sl frame buffer memory write enable 156 l_oe# o frame buffer memory outp ut enable 157 l_adsc# o, sl address status control mii management interface 120 m_mdc o mii management data clock 122 m_mdio i/o, u mii management data i/o i 2 c interface (seria l eeprom interface) 123 scl o, u, 5 i 2 c data clock 124 sda i/o, u, od, 5 i 2 c data i/o parallel port management interface 127 strobe i, u, s, 5 strobe pin 128 data0 i, u, 5 data pin 129 ack o, u, od, 5 acknowledge pin port 0 serial interface 23 m0_rxd i, u port 0 receive data
MVTX1100 data sheet 25 zarlink semiconductor inc. 24 m0_rxclk i, u port 0 receive clock 22 m0_crs_dv i, d port 0 carrier sense and data valid 20 m0_txd o port 0 transmit data 21 m0_txclk i port 0 transmit clock 19 m0_txen o port 0 transmit enable 12 m0_cls i, u port 0 collision detection 13 m0_link i, u port 0 link status 14 m0_duplex i, u port 0 full duplex select (half-duplex = 0) port 1 serial interface 30 m1_rxd i, u port 1 receive data 31 m1_rxclk i, u port 1 receive clock 29 m1_crs_dv i, d port 1 carrier sense and data valid 27 m1_txd o port 1 transmit data 28 m1_txclk i port 1 transmit clock 26 m1_txen o port 1 transmit enable 15 m1_cls i, u port 1 collision detection 16 m1_link i, u port 1 link status 17 m1_duplex i, u port 1 full-duplex select (half-duplex = 0) port 2 serial interface 37 m2_rxd i, u port 2 receive data 38 m2_rxclk i, u port 2 receive clock 36 m2_crs_dv i, d port 2 carrier sense and data valid 34 m2_txd o port 2 transmit data 35 m2_txclk i port 2 transmit clock 33 m2_txen o port 2 transmit enable 47 m2_cls i, u port 2 collision detection 48 m2_link i, u port 2 link status 49 m2_duplex i, u? port 2 full-duplex select (half-duplex = 0) port 3 serial interface 44 m3_rxd i, u port 3 receive data pin no(s). symbol type name & functions
MVTX1100 data sheet 26 zarlink semiconductor inc. 45 m3_rxclk i, u port 3 receive clock 43 m3_crs_dv i, d port 3 carrier sense and data valid 41 m3_txd o port 3 transmit data 42 m3_txclk i port 3 transmit clock 40 m3_txen o port 3 transmit enable 50 m3_cls i, u port 3 collision detection 51 m3_link i, u port 3 link status 52 m3_duplex i, u port 3 full-duplex select (half-duplex = 0) port 4 serial interface 64 m4_rxd i, u port 4 receive data 65 m4_rxclk i, u port 4 receive clock 63 m4_crs_dv i, u port 4 carrier sense and data valid 61 m4_txd o port 4 transmit data 62 m4_txclk i port 4 transmit clock 60 m4_txen o port 4 transmit enable 53 m4_cls i, u port 4 collision detection 54 m4_link i, u port 4 link status 55 m4_duplex i, u port 4 full-duplex select (half-duplex = 0) port 5 serial interface 71 m5_rxd i, u port 5 receive data 72 m5_rxclk i, u port 5 receive clock 70 m5_crs_dv i, d port 5 carrier sense and data valid 68 m5_txd o port 5 transmit data 69 m5_txclk i port 5 transmit clock 67 m5_txen o port 5 transmit enable 56 m5_cls i, u port 5 collision detection 57 m5_link i, u port 5 link status 58 m5_duplex i, u port 5 full-duplex select (half-duplex = 0) port 6 serial interface 78 m6_rxd i, u port 6 receive data pin no(s). symbol type name & functions
MVTX1100 data sheet 27 zarlink semiconductor inc. 79 m6_rxclk i, u port 6 receive clock 77 m6_crs_dv i, d port 6 carrier sense and data valid 75 m6_txd o port 6 transmit data 76 m6_txclk i port 6 transmit clock 74 m6_txen o port 6 transmit enable 88 m6_cls i, u port 6 collision detection 89 m6_link i, u port 6 link status 90 m6_duplex i, u port 6 full-duplex select (half-duplex = 0) port 7 serial interface 85 m7_rxd i, u port 7 receive data 86 m7_rxclk i, u port 7 receive clock 84 m7_crs_dv i, d port 7 carrier sense and data valid 82 m7_txd o port 7 transmit data 83 m7_txclk i port 7 transmit clock 81 m7_txen o port 7 transmit enable 91 m7_cls u port 7 collision detection 92 m7_link i, u port 7 link status 93 m7_duplex i, u port 7 full-duplex select (half-duplex = 0) port 0 rmii interface 24, 23 m0_rxd[1:0] i, u port 0 receive data 22 m0_crs_dv i, d port 0 carrier sense and data valid 21, 20 m0_txd[1:0] o port 0 transmit data 19 m0_txen o port 0 transmit enable port 1 rmii interface 31, 30 m1_rxd[1:0] i, u port 1 receive data 29 m1_crs_dv i, d port 1 carrier sense and data valid 28, 27 m1_txd[1:0] o port 1 transmit data 26 m1_txen o port 1 transmit enable port 2 rmii interface 38, 27 m2_rxd[1:0] i, u port 2 receive data pin no(s). symbol type name & functions
MVTX1100 data sheet 28 zarlink semiconductor inc. 36 m2_crs_dv i, d port 2 carrier sense and data valid 35, 34 m2_txd[1:0] o port 2 transmit data 34 m2_txen o port 2 transmit enable port 3 rmii interface 45, 44 m3_rxd[1:0] i, u port 3 receive data 43 m3_crs_dv i, d port 3 carrier sense and data valid 42, 41 m3_txd[1:0] o port 3 transmit data 40 m3_txen o port 3 transmit enable port 4 rmii interface 65, 64 m4_rxd[1:0] i, u port 4 receive data 63 m4_crs_dv i, d port 4 carrier sense and data valid 62, 61 m4_txd[1:0] o port 4 transmit data 60 m4_txen o port 4 transmit enable port 5 rmii interface 72, 71 m5_rxd[1:0] i, u port 5 receive data 70 m5_crs_dv i, d port 5 carrier sense and data valid 69, 68 m5_txd[1:0] o port 5 transmit data 67 m5_txen o port 5 transmit enable port 6 rmii interface 79, 78 m6_rxd[1:0] i, u port 6 receive data 77 m6_crs_dv i, d port 6 carrier sense and data valid 76, 75 m6_txd[1:0] o port 6 transmit data 74 m6_txen o port 6 transmit enable port 7 rmii interface 86, 85 m7_rxd[1:0] i, u port7 receive data 84 m7_crs_dv i, d port 7 carrier sense and data valid 83, 82 m7_txd[1:0] o port 7 transmit data 81 m7_txen o port 7 transmit enable port 8 mii interface 105, 104, 103, 102 m8_rxd[3:0] i, u port 8 receive data pin no(s). symbol type name & functions
MVTX1100 data sheet 29 zarlink semiconductor inc. 113, 112, 111, 110 m8_txd[3:0] o port 8 transmit data 109 m8_txen o port 8 transmit enable 97 m8_rxdv i, d port 8 receive data valid 100 m8_rxclk i, u port 8 receive clock 107 m8_txclk i/o, u port 8 transmit clock 114 m8_link i, u port 8 link status 116 m8_speed i/o, u port 8 speed select (100mb = 1) 115 m8_duplex i, u port 8 full-duplex select (half-duplex = 0) 98 m8_col i, u port 8 collision detect 118 m8_refclk o, u port 8 reference clock m8_refclk=1/2 m_clk port 8 serial interface 102 s8_rxd i, u port 8 serial receive data 100 s8_rxclk i, u port 8 serial receive clock 97 s8_crs_dv i, d port 8 serial carrier sense and data valid 110 s8_txd o port 8 serial transmit data 107 s8_txclk i port 8 serial transmit clock 109 s8_txen o port 8 serial transmit enable 98 s8_col i, u port 8 serial collision detect 114 s8_link i, u port 8 link status 115 s8_duplex i, u port 8 full-duplex select (half-duplex = 0) miscellaneous control pins 95 m_clk i reference clock for serial interface = 50 mhz50 ppm 148 sclk i system clock (50 - 80 mhz) 126 trunk_en i, d port trunking enable 142 resin# i, s reset pin 141 resetout# o phy reset pin 146, 145, 144, 143 mir_ctl[3:0] i/o, u port mirroring control (only for rmii mode) pin no(s). symbol type name & functions
MVTX1100 data sheet 30 zarlink semiconductor inc. test pins 125 test# manufacturing pin. leave as no connect (nc) 139 tmode# i/o, u manufacturing pin. puts device into test mode for ate test. leave as no connect (nc) 138, 137, 136, 135 tstout[7:4] o test outputs 134, 133, 132, 131 tstout[3:0] i/o, u test outputs power pins 3, 39, 73, 96, 130, 159, 184 vdd (core) input + 3.3 volt dc supply for core logic (7 pins) 11, 25, 59, 87, 101, 108, 119, 147, 152, 166, 175, 194, 202 vdd input +3.3 volt dc supply for i/o pads (13 pins) 18, 46, 80, 106, 140, 171, 198 vss (core) input ground for core logic (7 pins) 7, 32, 66, 94, 99, 117, 121, 149, 154, 162, 180, 189, 207 vss input ground for i/o pads (13 pins) pin no(s). symbol type name & functions
MVTX1100 data sheet 31 zarlink semiconductor inc. 13.1 strap options the strap options are relevant during the initial power-on period, when reset is asserted. during reset, MVTX1100 will examine the boot strap address pin to determine its va lue and modify the internal configuration of the chip accordingly. ?1? means pull up ?0? means pull down wi th an external 1 k ohm default value is 1, (all boot strap pins have internal pull up resistor). note 1: 1. if the MVTX1100 is configured from eeprom preset ( l_a[6] pulled down at reset), it will try to load its configuration from the eeprom. if the eeprom is blank or not preset, it will not boot up. the parallel port can be used to program the eeprom at any time. note 2: during normal power-up the MVTX1100 will run through an external sbram memory test to ensure that there are no memory interface problems. if a problem is detected, the chip will stop functioning. to facilitate board debug in the event that a sys tem stops functioning, the MVTX1100 can be put into a continuous sbram self test mode to allow an operator to determine if there are stuck pins in the memory interface (using network analyzer). pin no(s) symbol name & functions 206 (l_a[5]) memory size 1 - memory size = 256 kb, 0 - memory size = 512 kb 208 (l_a [6]) eeprom 1 - no eeprom installed 0 - eeprom installed 1 1 (l_a [7]) mii management via mdio 1 - enable 0 - disable 5, 4 (l_a [10:9]) xlink speed 11 - 100 mbps 10 - 200 mbps 01 - 300 mbps 00 - 400 mbps (0 - pull down, 1 - pull up) 160 (l_a[15]) ports 0-7 rmii/serial 1 - rmii mode for ports 0-7 0 - serial mode for ports 0-7 151 (l_a[17]) port 8 mii/seri al 1 - mii mode for port 8 0 - serial mode for port 8 150 (l_a[2]) link polarity link polarity for serial interface 1 - active low 0 - active high 204 (l_a[3]) fdx polarity full/half duplex polarity for serial interface 1 - active low 0 - active high 205 (l_a[4]) spd100 polarity speed polarity for serial interface 1 - active low 0 - active high 2 (l_a[8]) device id use in cascade mode only 133 (tst[2]) sbram self test for board/system manufacturing test 2 1 - disable 0 - enable
MVTX1100 data sheet 32 zarlink semiconductor inc. 14.0 dc electrical characteristics 14.1 absolute maximum ratings storage temperature -65 c to +150c operating temperature -40 c to +85c maximum junction temperature +125c supply voltage vdd with respect to v ss +3.0 v to +3.6 v voltage on 5v tolerant input pins -0.5 v to (vdd + 3.3 v) voltage on other pins -0.5 v to (vdd + 0.3 v) caution: stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposure to the absolute maximum ratings for extended periods may affect device reliability. 14.2 dc electrical characteristics vdd = 3.0 v to 3.6 v (3.3v +/- 10%) t ambient = -40c to +85c 14.3 recommended operating conditions symbol parameter description min. typ. max. unit f osc frequency of operation 50 66 80 mhz i dd v oh v ol supply current - @ 55 mhz, 8x100 m, 100% full duplex traffic (vdd = 3.3v) 580 ma output high voltage (cmos) 2.4 v output low voltage (cmos) 0.4 v v ih - ttl input high voltage (ttl 5 v tolerant) 2.0 vdd + 2.0 v v il - ttl input low voltage (ttl 5 v tolerant) 0.8 v i il input leakage current (0.1 v < v in < vdd) (all pins except those with internal pull-up/ pull- down resistors) 10 a i ol output leakage current (0.1 v < v out < vdd) 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance wi th 0 air flow 29.7 c/w ja thermal resistance with 1 m/s air flow 28.8 c/w ja thermal resistance with 2 m/s air flow 26.8 c/w jc thermal resistance between junction and case 12.6 c/w
MVTX1100 data sheet 33 zarlink semiconductor inc. 14.4 clock frequency specifications suggestion clock rate for various configurations: symbol parameter (hz) note: c1 sclk - core system clock input 50 m c2 m_clk - rmii port clock 50 m c3 m8_refclk - mii reference clock 25 m c4 l_clk - frame buffer memory clock 50 m l_clk = sclk c5 m_mdc - mii management data clock 1.56 m m_mdc = sclk/32 c6 scl - i 2 c data clock 50 k scl = m_clk/1000 input output configuration sclk m_clk (rmii) m8_ref l_clk m_mdc scl port 0-7 port 8 10 m rmii 10/100 m mii 50 m 50 m -- =sclk =sclk/32 50 k 100 m rmii not used 55 m 50 m -- =sclk =sclk/32 50 k 100 m rmii 10/100 m mii 60 m 50 m -- =sclk =sclk/32 50 k 100 m rmii 200 m mii 66.66 m 50 m 50 m =sclk =sclk/32 50 k 100 m rmii 300 m mii 75 m 50 m 75 m =sclk =sclk/32 50 k 100 m rmii 400 m mii 80 m 50 m 100 m =sclk =sclk/32 50 k
MVTX1100 data sheet 34 zarlink semiconductor inc. 15.0 ac timing characteristics 15.1 frame buffer memory interface: figure 6 - framer buffer memory interface timing symbol parameter 50 mhz note min. (ns) max. (ns) l1 l_d[31:0] input setup time 5 l2 l_d[31:0] input hold time 0 l3 l_d[31:0] output valid delay 1 8 c l = 30 pf l4 l_a[18:2] output valid delay 1 8 c l = 50 pf l6 l_adsc# output valid delay 1 8 c l = 50 pf l8 l_we# output valid delay 1 8 c l = 30 pf l9 l_oe# output valid delay 1 8 c l = 30 pf table 3 - frame buffer memory interface timing l_d[31:0]
MVTX1100 data sheet 35 zarlink semiconductor inc. 15.2 serial timing requirements 15.3 rmii timing requirements symbol parameter 50 mhz note: min. (ns) max. (ns) m1 m_[8:0]_[tx/rx]clk serial input clock m2 m[8:0]_rxd input setup time 4 m3 m[8:0]_rxd input hold time 1 m4 m[8:0]_crs_dv input setup time 4 m5 m[8:0]_txen output delay time 1 11 c l = 30 pf m6 m[8:0]_txd output delay time 1 11 c l = 30 pf m7 m[8:0]_link input setup time 4 table 4 - serial timing requirements symbol parameter 50 mhz note: min. (ns) max. (ns) m1 m_clk reference input clock m2 m[7:0]_rxd[1:0] input setup time 4 m3 m[7:0]_rxd[1:0] input hold time 1 m4 m[7:0]_crs_dv input setup time 4 m5 m[7:0]_txen output delay time 1 11 c l = 30 pf m6 m[7:0]_txd[1:0] output delay time 1 11 c l = 30 pf m7 m[7:0]_link input setup time 4 table 5 - rmii timing requirements
MVTX1100 data sheet 36 zarlink semiconductor inc. 15.4 mii timing requirements figure 7 - transmit timing *inf. = infinite table 6 - transmit timing requirements symbol parameter time unit min. max. 1 m8_txclk rise to m8_txd [3:0] inactive delay 5 20 ns 2 m8_txclk rise to m8_txd [3:0] active delay 5 20 ns 3 m8_txclk rise to m8_txen active delay 5 20 ns 4 m8_txclk rise of last m8_txd bit to m8_txen inactive delay 520ns 5 m8_txclk high wide 25 inf. ns 6 m8_txclk low wide 25 inf. ns m8_txclk input rise time require 5 ns m8_txclk input fall time require 5 ns
MVTX1100 data sheet 37 zarlink semiconductor inc. figure 8 - receive timing symbol parameter time unit min. max. 1 m8_rxd[3:0] low input setup time 10 ns 2 m8_rxd[3:0] low input hold time 5 ns 3 m8_rxd[3:0] high input setup time 10 ns 4 m8_rxd[3:0] high input hold time 5 ns 5 m8_rxdv low input setup time 10 ns 6 m8_rxdv low input hold time 5 ns 7 m8_rxdv high input setup time 10 ns 8 m8_rxdv high input hold time 5 ns 9 m8_rxclk high wide 25 inf. ns 10 m8_rxclk low wide 25 inf. ns m8_rxclk input rise time require 5 ns m8_rxclk input fall time require 5 ns table 7 - receive timing requirements
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes: 3. the top package body size may be smaller than the bottom package body size by a max. of 0.15 mm. 1. pin 1 indicator may be a corner chamfer, dot or both. 2. controlling dimensions are in millimeters. 4. dimension d1 and e1 do not include mould protusion. notes: pin 1 index corner e1 e d d1 l a1 a2 a = 0-7
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